Communication Mechanism and Error Detection of CAN Bus

Communication Mechanism and Error Detection of CAN Bus

  1. Communication mechanism of CAN bus

The CAN bus is essentially a priority competition non-destructive arbitration protocol based on the carrier sense multiple access with collision detection (CSMA/CD) mechanism. The CAN bus can realize multi-master peer-to-peer communication, that is, when each node on the bus detects that the bus is in an idle state, it can start sending, otherwise it must wait, and “monitor” the bus state while sending. When multiple nodes start sending at the same time, a conflict occurs, and the sending node will detect the conflict at this time. The CAN bus adopts priority competition non-destructive arbitration to solve the conflict problem, that is, when a conflict occurs, the information is arbitrated according to the priority, the information with high priority continues to be sent, and the information with low priority loses the arbitration and changes to the receiving state. It is carried out bit by bit until the highest priority information obtains the right to use the bus and starts to send the content of subsequent frames.

CAN bus
CAN bus

The CAN bus uses wire-AND logic, that is, when the dominant bit binary “0” collides with the recessive bit binary “1”, the result of 0&1=0 will be generated. Therefore, the bit value of 0 has higher priority than the bit value of 1. Each CAN message frame has a unique 11-bit or 29-bit binary identifier ID. The smaller the identifier ID of the visible information, the greater the priority of the information, and the greater the chance of winning the bus use right to continue to complete the transmission in the conflict.

  1. Error detection of CAN bus

2.1. Error types and definitions

There are 5 types of errors in the CAN bus.
(1) Bit error. The node that is sending a bit to the bus is also detecting the bus. When the detected bit value is different from the sent bit value, a bit error is detected. The exception to this is when a dominant bit is detected by sending a recessive bit during the filling bit stream of the arbitration field or in the acknowledgement gap, it is not regarded as a bit error. A transmitter that sends an acknowledgement error flag is not regarded as a bit error when it detects a significant bit.

(2) Filling errors. A stuffing error is detected when the sixth consecutive bit of the same level occurs in a frame field encoded using the bit stuffing method.
(3) CRC error. The CRC sequence consists of the result of the transmitter’s CRC calculation. The receiver calculates the CRC in the same way as the transmitter. A CRC error is detected when the calculated CRC sequence is not equal to the received sequence.

(4) Form is wrong. Form errors are detected when the fixed format bits contain one or more illegal bits. The exception is that the receiver does not interpret a “dominant” bit as a formal error when it detects the last bit at the end of the frame.

(5) The response is wrong. An acknowledgment error is detected when no “dominant” bit is detected during the transmitter ACK slot.

Although the above five kinds of error detection greatly improve the data reliability of the CAN bus, if there is a defective node in the system, it will continuously send error frames, causing the bus to be blocked. In order to prevent this from happening, CAN provides a method of distinguishing between transient disturbances and permanent faults, that is, fault definition. For fault definition, each node unit on the bus is provided with two counters: send error counter and receive error counter. Error counters are corrected according to a series of rules. Any node in the network will determine the state of the node according to the value of its error counter, and the various states can also be dynamically migrated according to the value of the error counter.

Depending on the value of the error counter, the node may be in the following three states.
(1) “Error activated” state. A node in the “error active” state can normally participate in bus communication and sends an active error flag when an error is detected. The active error flag consists of 6 consecutive “dominant” bits and obeys padding rules and all fixed formats.

(2) “Error recognition” status. A node in the “false acknowledgement” state shall not send an active error flag, it participates in bus communication, but when an error is detected, it sends an acknowledgement error flag consisting of 6 consecutive “recessive” bits.

(3) “Bus off” state. When a node is closed to the bus, it is in the “bus closed” state. In the “bus off” state, the node neither sends nor receives any frames. A node cannot be released from the “bus off” state unless requested by the user.

2.2. Error checking of CAN bus

(1) The node whose error bit is in the sending state monitors each bit of the bus. If it is detected that the sending bit is inconsistent with the detection result, a bit error is reported. Except for the following cases: In the arbitration domain, recessive can be written as dominant, which means that the node loses priority: in the response gap, only the receiving node can acknowledge the bit error.

(2) Bit stuffing (insertion) error. The following bit fields use bit stuffing (insertion) technology: frame start field, arbitration field, control field, data field, CRC field. There are two situations where stuffing errors may occur: more than 5 consecutive bits of the same polarity are generated due to interference, which can be detected by all nodes; one or more bits before the stuffing bits are erroneous due to interference. This error is not considered by the receiver to be a padding error, and other error detection mechanisms can detect such errors.

(3) CRC error. All receiving nodes will perform CRC check on the received information. The CAN controller uses BCH (Bose, Ray-Chaudhuri, Hocquenghem) code, plus parity check, which has the following characteristics: the maximum code length is 127 bits; the longest The information is 112 bits; the CRC length is 15 bits; the Hamming distance is d-6, so d-1 random errors can be detected.

It should be noted that the error checking function of the CAN bus node has been solidified in the silicon chip, and the realization of this function is realized by hardware. After the node’s receiving error is detected, the error counter is incremented by 1; after the node’s transmission error is detected, the error counter is incremented by 8. Regardless of a send or receive error, the node will immediately terminate the transfer on the bus and send an error frame. When the node sends or receives a correct data frame, the corresponding error count register is decremented by 1. When all error count registers return to 0, the CAN controller can return to normal mode.

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